Semiconductor integrated circuit (IC) fabrication involves forming multiple material layers with designed patterns on a semiconductor wafer. Each layer has to be aligned with previous layers such that the formed circuit can function properly. Various marks are used for this purpose. For example, alignment marks are used for alignment between a photomask and the semiconductor wafer. In another example, overlay marks are used to monitor overlay deviation between the layers on the wafer. As semiconductor technology continues progressing to circuit layouts having smaller feature sizes, the alignment requirement becomes more stringent and the alignment/overlay marks are expected to take less wafer area. Stacked marks are used with various blocking layers. For example, a blocking layer is inserted between a top pair of overlay marks and a bottom pair of overlay marks stacked. Furthermore, a minimum vertical spacing between the bottom pair of overlay marks and the blocking layer to ensure effective signal blocking. In this situation, extra processing steps and more chip area are needed, resulting higher manufacturing cost and chip cost. It is desired, therefore, to provide a method and a structure for monitoring and controlling alignment and overlay with less footprint.